integrated telecom express, inc. 1 I90135 product data sheet version 1.2 (june 1999) I90135-adsl digital chip features ! ansi t1.413 issue 2 standard dmt modem with embedded, bypassable, atm framer ! byte interface or standard utopia level 1 and level 2 atm interfaces ! main functions include: receive direction: - rotor and adaptive frequency domain equalizing - demapping of dmt carriers into a digital bitstream, including 4d trellis coding - error and noise monitoring on individual carriers and pilot tones - reed-solomon decoding and deinterleaving - adsl deframing - atm cell-specific deframing (can be bypassed) - 144-pin pqfp package - power consumption 1 watt at 3.3v transmit direction: - atm cell-specific framing - adsl framing - reed-solomon encoding - mapping of digital bitstream onto dmt carriers - rotor and frequency domain gain correction general description itex's I90135 is the dmt modem and atm framer of the apollo series rate adaptive adsl chipset. the I90135 is intended to be used in combination with i80134 analog front end. in addition, the control function of the chipset can be performed on a dedicated external controller (see figure 1.1) or on host/control software eliminating the need for a microcontroller (see figure 1.2). the I90135 may be used in both atu-c (central office) and atu-r (remote) applications. the chip provides both a cell- based utopia level 1 and 2 atm data interface to the host and a non-atm synchronous bit stream. the I90135 performs the dmt modulation, demodulation, reed-solomon encoding, bit interleaving, and 4d trellis coding. the I90135 is in a 144-pin pqfp package.
integrated telecom express, inc. 2 I90135 product data sheet version 1.2 (june 1999) I90135 dmt modem and atm framer i80134 analog front end pots splitter line i90188 pci controller figure 1.2: general block diagram (controllerless configuration) adsl controller software host based a/b utopia pci afe I90135 dmt modem and atm framer i80134 analog front end atm utopia 1 & 2 interface hybr id pots splitter line stm bitstream microprocessor or dedicated controller flash ram figure 1.1: general block diagram a/b
integrated telecom express, inc. 3 I90135 product data sheet version 1.2 (june 1999) block diagram introduction the following essential describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. dsp front end the dsp front end contains four parts in the receive direction: the input selector, the analog front end interface, the decimator and the time equalizer. the input selector is used internally to enable test loopbacks inside the chip. the analog front end interface transfers 16-bit word, multiplexed on four input/output signals. as a result, four dock cycles are needed to transfer one word. the decimator receives the 16-bit samples at 8.8 mhz (as sent by the analog front end chip) and reduces this rate to 2.2 mhz. test module data symbol timing unit vcxo dsp front-end fft/ ifft rotor trellis coding mapper/ demapper generic tc reed/ solomon atm specific tc reset controller interface interface module clock test signals afe interface slap utopia reset controller bus general purpose i/os figure 2: I90135 block diagram
integrated telecom express, inc. 4 I90135 product data sheet version 1.2 (june 1999) the tme equalizer (teq) module is an fir filter with programmable coefficients. its main purpose is to reduce the effect of inter-symbol interferences (isi) by shortening the channel impulse response. both the decimator and teq can be bypassed. in the transmit direction, the dsp front end includes: sidelobe filtering, clipping, delay equalization, and interpolation. the sidelobe filtering and delay equalization are implemented by iir filters, reducing the effect of echo in fdm systems. clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the afe. the interpolator receives data at 2.2 mhz and generates samples at a rate of 8.8 mhz. dmt modem this computational module is a programmable dsp unit. its instruction set enables functions like fft, ifft, scaling, rotor, and frequency equalization (feq). this block implements the core of the dmt algorithm as specified in ansi t1.413. in the rx path, the 51 2-point fft transforms the time domain dmt symbol into a frequency domain representation, which can be further decoded by the subsequent demapping stages. after the first stage time domain equalization and fft block an essentially ici (intercarrier interferences)-free carrier information stream has been obtained. this stream is still affected by carrier-specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. to compensate for these effects, the fft is followed by a frequency domain equalizer (feq) and a rotor (phase shifter). in the tx path, the ifft transforms the dmt symbol generated in the frequency domain by the mapper into a time domain representation. the ifft block is proceed by a fne tune gain and a rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). the fft module is a slave dsp engine controlled by the transceiver controller. it works off line and communicates with the other blocks via buffers controlled by the dstu block. the dsp executes a program stored in a ram area, a very flexible implementation open for future enhancements. dpll the digital pll module receives a metric for the phase error of the pilot tone. in general, the clock frequencies at the transmitter and receiver do not match exactly. the phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. various processes can use this estimate to deal with the frequency mismatch. in particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (rotor). larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence.
integrated telecom express, inc. 5 I90135 product data sheet version 1.2 (june 1999) mapper/demapper, monitor, trellis coding, feq update the demapper converts the constellation points computed by the fft to a block of bits. this essentially consists in identifying a point in a 2d qam constellation plane. the demapper supports trellis coded demodulation and provides a viterbi maximum likelihood estimator. when the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. in the transmit direction, the mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the ifft block. the trellis encoder generates redundant bits to improve the robustness of the transmission, using a 4-dimensional trellis coded modulation scheme. the monitor computes error parameters for carriers specified in the demapper process. those parameters can be used for updates of adaptive filters coefficient, clock phase adjustments, error detection, etc. a series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. pin diagram vss 1 ad_0 2 ad_1 3 ad_2 4 vdd 5 ad_3 6 ad_4 7 vss 8 ad_5 9 ad_6 10 vdd 11 ad_7 12 ad_8 13 ad_9 14 vss 15 ad_10 16 ad_11 17 vdd 18 ad_12 19 vss 20 pclk 21 vdd 22 ad_13 23 ad_14 24 ad_15 25 vss 26 be1 27 ale 28 vdd 29 csb 30 wr_rdb 31 rdyb 32 obc_type 33 intb 34 resetb 35 vss 36 108 vdd 107 slt_req_f 106 slt_dat_s0 105 slt_dat_s1 104 slt_dat_f0 103 slt_dat_f1 102 vss 101 slt_frame_f 100 slap_clock 99 slr_val_f 98 slr_dat_f0 97 slr_dat_f1 96 slr_val_s 95 vdd 94 slr_dat_s0 93 slr_dat_s1 92 slr_frame_s 91 vss 90 slr_frame_f 89 u_tx_addr_0 88 u_tx_addr_1 87 u_tx_addr_2 86 vdd 85 u_tx_addr_3 84 u_tx_addr_4 83 u_tx_data_0 82 u_tx_data_1 81 vdd 80 u_tx_data_2 79 u_tx_data_3 78 u_tx_data_4 77 u_tx_data_5 76 vdd 75 u_tx_data_6 74 u_tx_data_7 73 vss vdd 144 aftxd_3 143 aftxd_2 142 vss 141 aftxd_1 140 aftxd_0 139 iddq 138 vdd 137 aftxed_3 136 aftxed_2 135 vss 134 aftxed_1 133 aftxed_0 132 vdd 131 ctrldata 130 mclk 129 clwd 128 vss 127 afrxd_3 126 afrxd_2 125 afrxd_1 124 afrxd_0 123 vdd 122 pdown 121 gp_out 120 testse 119 trstb 118 vss 117 tck 116 vdd 115 tms 114 tdo 113 tdi 112 slt_frame_s 111 slt_req_s 110 vss 109 37 vdd 38 u_rxdata_0 39 u_rxdata_1 40 vss 41 u_rxdata_2 42 u_rxdata_3 43 vdd 44 u_rxdata_4 45 u_rxdata_5 46 vss 47 u_rxdata_6 48 u_rxdata_7 49 vdd 50 u_rx_addr_0 51 u_rx_addr_1 52 u_rx_addr_2 53 u_rx_addr_3 54 vss 55 u_rx_addr_4 56 gp_in_0 57 vdd 58 gp_in_1 59 vss 60 u_tx_refb 61 u_rx_refb 62 vdd 63 u_rxclk 64 u_rxsoc 65 u_rx_clav 66 u_rxenbb 67 vss 68 u_txclk 69 u_txsoc 70 u_tx_clav 71 u_txenbb 72 vdd afe test slap utopia obc figure 3: pinout (topside view)
integrated telecom express, inc. 6 I90135 product data sheet version 1.2 (june 1999) pin assignment and description pin mnemonic type supply driver bs description 1vss 0 volt ground 2 ad_0 b vdd bd8scr b micro processor interface 3 ad_1 b vdd bd8scr b address / data 1 4 ad_2 b vdd bd8scr b address / data 2 5 vdd +3.3 volts power supply 6 ad_3 b vdd bd8scr b address / data 3 7 ad_4 b vdd bd8scr b address / data 4 8vss 0 volt ground 9 ad_5 b vdd bd8scr b 10 ad_6 b vdd bd8scr b 11 vdd +3.3 volts power supply 12 ad_7 b vdd bd8scr b 13 ad_8 b vdd bd8scr b 14 ad_9 b vdd bd8scr b 15 vss 0 volt ground 16 ad_10 b vdd bd8scr b 17 ad_11 b vdd bd8scr b 18 vdd +3.3 volts power supply 19 ad_12 b vdd bd8scr b 20 vss 0 volt ground 21 pclk vdd ibuf i processor clock 22 vdd +3.3 volts power supply 23 ad_13 b vdd bd8scr b 24 ad_14 b vdd bd8scr b 25 ad_15 b vdd bd8scr b 26 vss 0 volt ground 27 be1 i vdd ibuf i address [1] input 28 ale i vdd ibuf c used to latch the address of the internal register to be accessed 29 vdd +3.3 volts power supply 30 csb i vdd ibuf i chip selected to respond to bus cycle 31 wr_rdb i vdd ibuf i specifies the direction of the access cycle 32 rdyb oz vdd bt4cr o 33 obc_type i-pd vdd ibuf i atc mode selection 34 intb o vdd ibuf o requests atc interrupts service 35 resetb i vdd ibuf i hard reset 36 vss 0 volt ground 37 vdd +3.3 volts power supply 38 u_rxdata_0 oz vdd bd8scr b utopia rx data 0 39 u_rxdata_1 oz vdd bd8scr b utopia rx data 1
integrated telecom express, inc. 7 I90135 product data sheet version 1.2 (june 1999) pin mnemonic type supply driver bs description 40 vss 0 volt ground 41 u_rxdata_2 oz vdd bd8scr b utopia rx data 2 42 u_rxdata_3 oz vdd bd8scr b utopia rx data 3 43 vdd +3.3 volts power supply 44 u_rxdata_4 oz vdd bd8scr b utopia rx data 4 45 u_rxdata_5 oz vdd bd8scr b utopia rx data 5 46 vss 0 volt ground 47 u_rxdata_6 oz vdd bd8scr b utopia rx data 6 48 u_rxdata_7 oz vdd bd8scr b utopia rx data 7 49 vdd +3.3 volts power supply 50 u_rxaddr_0 i vdd ibuf i utopia rx address 0 51 u_rxaddr_1 i vdd ibuf i utopia rx address 1 52 u_rxaddr_2 i vdd ibuf i utopia rx address 2 53 u_rxaddr_3 i vdd ibuf i utopia rx address 3 54 vss 0 volt ground 55 u_rxaddr_4 i vdd ibuf i utopia rx address 4 56 gp_in_0 i-pd vdd ibufdq i general purpose input 57 vdd +3.3 volts power supply 58 gp_in_1 i-pd vdd ibufdq i general purpose input 1 59 vss 0 volt ground 60 u_rxrefb o vdd ibuf o 8 khz clock to atm device 61 u_txrefb i vdd bt4cr i 8 khz from network 62 vdd vss +3.3 volts power supply 63 u_rxclk i vdd ibuf receive interface utopia clock 64 u_rxsoc o-z vdd bd8scr receive interface start of cell indication 65 u_rxclav o-z vdd bd8scr 66 u_rxenbb i vdd ibuf 67 vss 0 volt ground 68 u_txclk i vdd ibuf transmit interface utopia clock 69 u_txsoc i vdd ibuf transmit interface start of cell indication 70 u_txclav o-z vdd bd8scr 71 u_txenbb i vdd ibuf utopia tx enable 72 vdd +3.3 volts power supply 73 vss 0 volt ground 74 u_txdata_7 i vdd ibuf i utopia tx data 7 75 u_txdata_6 i vdd ibuf i utopia tx data 6 76 vdd +3.3 volts power supply 77 u_txdata_5 i vdd ibuf i utopia tx data 5 78 u_txdata_4 i vdd ibuf i utopia tx data 4 79 u_txdata_3 i vdd ibuf i utopia tx data 3 80 u_txdata_2 i vdd ibuf i utopia tx data 2 81 vdd +3.3 volts power supply
integrated telecom express, inc. 8 I90135 product data sheet version 1.2 (june 1999) pin mnemonic type supply driver bs description 82 u_txdata_1 i vdd ibuf i utopia tx data 1 83 u_txdata_0 i vdd ibuf i utopia tx data 0 84 u_txaddr_4 i vdd ibuf i utopia tx address 4 85 u_txaddr_3 i vdd ibuf i utopia tx address 3 86 vdd +3.3 volts power supply 87 u_txaddr_2 i vdd ibuf i utopia tx address 2 88 u_txaddr_1 i vdd ibuf i utopia tx address 1 89 u_txaddr_0 i vdd ibuf i utopia tx address 0 90 slr_frame_f o vdd bt4cr frame identifier fast 91 vss 0 volt ground 92 slr_frame_s o vdd bt4cr frame identifier interleaved 93 slr_data_s_1 o vdd bt4cr data interleave 1 94 slr_data_s_0 o vdd bt4cr data interleave 0 95 vdd +3.3 volts power supply 96 slr_val_s o vdd bt4cr data valid indicator interleaved 97 slr_data_f_1 o vdd bt4cr data fast 1 98 slr_data_f_0 o vdd bt4cr data fast 0 99 slr_val_f o vdd bt4cr data valid indicator fast 100 slap_clock o vdd bt4cr clock for slap i/f 101 slt_frame_f o vdd bt4cr start of frame indicator fast 102 vss 0 volt ground 103 slt_data_f_1 i vdd ibufdq fast data 1 104 slt_data_f_0 i vdd ibufdq fast data 0 105 slt_data_f_1 i vdd ibufdq data 1 106 slt_data_f_0 i vdd ibufdq data 0 107 slt_req_f o vdd bt4cr byte request fast 108 vdd +3.3 volts power supply 109 vss 0 volt ground 110 slt_req_s o vdd bt4cr byte request interleaved 111 slt_frame_s o vdd bt4cr start of frame indication interleaved 112 tdi i-pu vdd ibufdq jtag i/p 113 tdo oz vdd bt4cr jtag o/p 114 tms i-pu vdd ibufdq jtag mode select 115 vdd +3.3 volts power supply 116 tck i-pd vdd ibufdq jtag clock 117 vss 0 volt ground 118 trstb i-pd vdd ibufdq jtag reset 119 testse i vdd ibuf none enables scan test mode 120 gp_out o vdd bd8scr o general purpose analog output 121 pdown o vdd bt4cr o power down analog front end 122 vdd +3.3 volts power supply 123 afrxd_0 i vdd ibuf i receive data nibble 124 afrxd_1 i vdd ibuf i receive data nibble
integrated telecom express, inc. 9 I90135 product data sheet version 1.2 (june 1999) pin mnemonic type supply driver bs description 125 afrxd_2 i vdd ibuf i receive data nibble 126 afrxd_3 i vdd ibuf i receive data nibble 127 vss 0 volt ground 128 clwd i vdd ibuf i start of word indication 129 mclk i vdd ibuf c master clock 130 ctrldata o vdd bt4cr o serial data transmit channel 131 vdd +3.3 volts power supply 132 aftxed_0 o vdd bt4cr o transmit echo nibble 133 aftxed_1 o vdd bt4cr o transmit echo nibble 134 vss 0 volt ground 135 aftxed_2 o vdd bt4cr o transmit echo nibble 136 aftxed_3 o vdd bt4cr o transmit echo nibble 137 vdd +3.3 volts power supply 138 iddq i vdd ibuf none test pin, active high 139 aftxd_0 o vdd bt4cr o transmit data nibble 140 aftxd_1 o vdd bt4cr o transmit data nibble 141 vss 0 volt ground 142 aftxd_2 o vdd bt4cr o transmit data nibble 143 aftxd_3 o vdd bt4cr o transmit data nibble 144 vdd +3.3 volts power supply package the I90135 is available in a 144-pin pqfp package. ?1998 itex ? and alcatel alsthom. itex ? is a trademark of integrated telecom express, inc. all other trademarks are the sole property of their respective owners. windows is a trademark of microsoft corporation. itex's standard terms and conditions, available upon request, apply to all sales. all specifications are subject to change without notice.
|
